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    Home » AI’s Real Bottleneck Is Not the Chip. It Is the Gap Between Chips

    AI’s Real Bottleneck Is Not the Chip. It Is the Gap Between Chips

    Artificial Intelligence August 1, 2026Updated:September 8, 20266 Mins Read
    Optical fibre links connecting computer chips inside a data centre rack
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    By Mansoor Ali, Technical Editor at PenPonder

    Buy more GPUs. Build a bigger data centre. That has been the answer to almost every AI speed problem for years.

    It works. It is also getting expensive. And it is running into a limit that more chips cannot fix.

    The limit is not the chip. It is the wiring between chips.

    A team at Peking University put a number on that. They swapped the copper links between chips for light. On one small AI task, their setup ran more than 100 times faster than a GPU. It used about one ninth of the computing power.

    The headlines picked up the 100x. Most of them skipped the part that actually matters.

    Table of Contents show
    1 What really slows a big AI job down
    2 What the Peking University team actually built
    3 How to read the 100x number
    4 Why light, and why now
    5 What this means if you are not building chips
    6 Sources

    What really slows a big AI job down

    Think of a neural network as a five step assembly line. Each step needs the output of the step before it.

    A GPU does not run it like an assembly line. It finishes layer one. It writes the result out to memory. Then it reads that same result back in for layer two.

    Every round trip costs time. While the data moves, parts of the chip sit idle doing nothing. Engineers call this the memory wall.

    Now scale it up. A large AI job runs across thousands of chips at once. Chip A finishes its share and hands it to chip B. If that handoff is slow, the whole cluster waits on it.

    So you can buy the fastest chips made. You still lose most of the benefit in traffic.

    What the Peking University team actually built

    They did not build a faster processor. They built better roads between processors.

    The hardware has two custom pieces:

    • A silicon photonic transceiver running at 400 gigabits per second. It turns electrical signals into light, and light back into electrical signals.
    • A 16 by 16 optical switch chip that routes the light between computing nodes. Together the switch carries up to 6.4 terabits per second in total.

    One detail is easy to skip past. The switch loses under 5 decibels of signal in total, including coupling loss. Low loss means the light does not need boosting on the way. No boosting means no extra hardware and no extra delay.

    The test itself was small and specific. Five FPGA chips. A five layer neural network that cleans noise out of images. Each chip ran one layer.

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    Instead of writing to memory after each layer, every chip passed its output straight down the optical link to the next one. A real assembly line. The five chip setup ran at 94.7 percent of its theoretical peak, which is close to as good as that design gets.

    FPGAs are not GPUs. An FPGA is a chip you rewire for one specific job. That is part of why the comparison numbers look so dramatic.

    ItemDetail
    JournalNational Science Review (published May 19, 2026)
    Lead institutionPeking University
    Chips usedFPGAs, five of them in the test
    Optical transceiver400 Gbps silicon photonic
    Optical switch16 x 16 non blocking, 6.4 Tbps total bandwidth
    Signal lossUnder 5 dB including coupling
    Test taskFive layer neural network, image denoising
    Headline resultOver 100x faster inference, about one ninth the compute
    System efficiency94.7 percent of theoretical peak

    How to read the 100x number

    It is a real result. It is also a narrow one.

    The task used 5 by 5 convolution kernels. That is a modest workload by current AI standards. It is nothing like running a large language model.

    The 100x figure comes from a comparison against one chosen GPU baseline on that one task. Change the task and the number changes.

    The authors are honest about the next problem too. Growing this to the full 16 chip design needs faster input and output on the FPGAs themselves. That work is not done.

    So no, ChatGPT is not about to get 100 times faster. And no data centre can bolt this on next quarter. This is a lab system, not a product.

    Why light, and why now

    Light travels fast and wastes little energy over distance. Copper does neither once you push enough data through it.

    The obvious question is why nobody has done this already. The answer is that steering light on and between chips is genuinely hard. Silicon photonics has been an active research field for years for exactly that reason.

    There is a supply chain angle as well. Silicon photonics can be made on older, mature production lines. It does not need the newest lithography machines, which are the ones export controls target. Analysts have pointed to photonics as a real front in the chip competition between the US and China.

    Chinese labs have had a run of these results lately. On the software side, Moonshot AI made a similar point with its Kimi K3 open source release. The pattern is the same: work around the hardware limit instead of buying past it.

    What this means if you are not building chips

    Nothing changes for you this year. That part is simple.

    The longer view is more interesting. Power and cooling are now a hard limit on how big data centres can get. Electricity costs money. So does the concrete.

    If chips can talk to each other faster, cheaper hardware can finish the same work. That is a very different spending path from buying more of the most expensive processors on the market. Companies running AI at scale will notice that before anyone else does.

    The term to watch is co-packaged optics. It means putting the optical parts in the same package as the processor, instead of off to the side. The Peking team names it as the step that would move this from lab bench to real systems.

    China’s research pipeline is worth tracking on the hardware side generally. We covered another example in our piece on China’s first approved brain computer interface. For wider context on where AI hardware and models are heading, start with our AI guide.

    Sources

    • Science China Press release on the on-chip all-optical supernode, which lists the hardware specs and test setup
    • The paper itself in National Science Review (DOI 10.1093/nsr/nwag282)
    • South China Morning Post on the research team and the FPGA design
    • VnExpress International, which covers the memory wall detail and the limits of the test

    Disclaimer: This article reports on published research and is for general information only. It is not technical, investment, or purchasing advice. Findings from a single lab study can change as other researchers try to repeat them. PenPonder verifies every claim against primary sources and corrects errors when readers flag them.

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    Mansoor Ali
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    Mansoor Ali is the Technical Editor at PenPonder and the founder of MajestySEO. With over 14 years of hands-on experience in technical SEO, WordPress architecture, and site security, he specializes in building and recovering digital assets. He founded his agency in 2012 and writes strictly from personal experience, breaking down complex technical guidelines into steps that actually work in the real world.

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